In the semiconductor industry, integrated circuits are typically formed on wafers, wherein a plurality of semiconductor chips on the same wafer is formed simultaneously. The semiconductor chips are then sawed from the wafers. Since semiconductor chips are typically small and fragile, they need to be packaged before being used.
FIG. 1 illustrates a conventional package, which includes a semiconductor chip (die) 2 bonded to a package substrate 4, for example, through solder bumps 6. Package substrate 4 includes a core 8 and a plurality of interconnect layers built up on both sides of core 8. Die 2 and core 8 are separated by interconnect layers. On a side of core 8 opposite the side where die 2 is attached, ball grid array (BGA) balls 10 are formed for connecting package substrate 4 to other electrical components, such as a motherboard. Die 2 and BGA balls 10 are electrically coupled through metal lines and vias formed in the interconnect layers. Vias 12 are formed in core 8 to make electrical connection from one side of core 8 to another.
The conventional packages suffer drawbacks. First, forming solder bumps 6 involves a high cost. The packaging process also suffers high yield lost due to failed solder bump connections. Second, die 2 typically has a coefficient of thermal expansion (CTE) of about 2.3 to 4.2. Core 8, on the other hand, is typically formed of bismaleimide triazine (BT), which has a CTE of about 15. The significant CTE mismatch causes stresses applied on die 2 and solder bumps 6, which, under thermal cycles, may cause warpage of die 2 and/or the failure of the solder bump connections. Third, due to the use of core 8, the thickness of the package is increased. The total thickness of the entire package, including BGA balls 10, package substrate 4 and die 2, may reach 2.3 mm, which will be too thick for future requirements. Therefore, new packaging structures and methods are needed.